Method on scan chain reordering for lowering VLSI power consumption

ABSTRACT

A method for reordering a scan chain so that the given constraints are met and the peak power dissipation is minimized and disclosed. The constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The developed tool can be embedded into the existing VLSI design flow for low-power circuit designs. Furthermore, the characteristics are quickly judging if the problem has corresponding feasible solutions and searching the optimal solution. Given the scan chain declaration data and the scan pattern data, the modified ones, which satisfy the constraints, can be obtained.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a method for reordering a scan chain, and moreparticularly to a method for reordering a scan chain that minimizes thepeak power consumption of Very Large Scale Integration (VLSI) Circuits.

2. Description of Related Art

Along with VLSI Circuits designed more complex, higher densitytransistors and lower power consumption components are used widely.Designing a lower power consumption VLSI circuit is the latest trend.

In recent years, a topic for discussion of the Design for Testability(DFT) of VLSI against the power dissipation has been widely regarded. Ageneral designed circuit is operated in two modes: Normal Mode and TestMode. In the test mode, the test patterns for testing combinatory logiccircuit are stored in the scan register of system. Some of the testpatterns may not appear in the normal mode at all. In other words, thepotential conversion of register that may not happen in the normal modepossibly and happen in the test mode. Therefore, the test pattern in thetest mode will lead to high power dissipation in the circuit ofregister. In another aspect, the test pattern is generated by AutomaticTest Pattern Generator (ATPG) that is designed with DFT and will testthe majority of circuits as possibly as it can and make the potential ofthe circuits frequently convert, thereby causing the condition circuitto be more deteriorated.

It is noteworthy that an oversized peak value of power dissipation willlead to a malfunction of the circuit during testing and namely, a chipnormally operating in the normal mode may not be qualified by ATPG.There are various ways of improvement of reducing the: power dissipationin the testing mode. Some conventional technologies (R. M. Chou, K. K.Saluja, and V. D. Agrawal, “Scheduling tests for VLSI systems underpower constraints,” IEEE Trans. VLSI, vol. 5, no. 2, pp. 175-184, 1997and S. Wang and S. K. Gupta, “ATPG for heat dissipation minimizationduring test application,” in Proc. IEEE Int. Test Conf., 1994, pp.250-257) are used ATPG to create the optimum test patterns capable ofreducing the power dissipation.

Further, re-ordering the Scan Chain register can also effectively reducethe power dissipation at the time of the potential conversion. As shownin FIG. 1A, if the test pattern data, 0101, is input to a 4-bit scanchain, ABCD, then it must take 4 times of shifts during total 10 timesof the potential state conversion occur, wherein the potential stateconversion of each bit occurs in the case of the last shift. If there-ordered scan chain is BDAC, as shown in FIG. 1B, only 2 times ofpotential state conversion occur in the course of 4 times of shifts. Aconventional technology (V Dabholkar, S. Chakravarty, I. Pomeranz, andS. Reddy, “Techniques for minimizing power dissipation in scan andcombinational circuits during test application,” IEEE Trans. CAD, vol.17, no. 12, pp. 1325-1333, 1998) provides two algorithms: RandomOrdering and Simulated Annealing. However, if there is much test patterndata and there are large amounts of registers, ordering of a largenumber of registers is necessary so as to highly reduce the powerdissipation as possibly as it can, thereby causing uneconomicalsituation. However, simulated annealing an initial state that possiblyis close to minimum power dissipation, or else it may take long time toperform the algorithm, which is not practical. Regarding this problem,this invention provides a research on scan chain ordering that fastmeets the limits of design specifications. Also, still anotherconventional technology (O. Sinanoglu, I. Bayraktaroglu, and A.Orailoglu, “Scan power reduction through test data transition frequencyanalysis,” in Proc. Int. Test Conf., 2002, pp. 844-850) is provided toinsert an inverter into the parts of the positions of the scan chain,thereby reducing the probability of the potential conversion for areduction of power dissipation. However, the insertion of the inverterwill change the circuit placement formerly completed in the physicaldesign of VLSI circuit, so that this practice is not involved in theresearch field of this invention. Next another conventional technology(S. Ghosh, S. Basu, and N. A. Touba, “Joint minimization of power andarea in scan testing by scan cell reordering,” in Proc. IEEE ComputerSociety Annual Symposium on VLSI, 2003, pp.) seeks for an optimum scanchain ordering using Greedy Algorithm, and considers the connectiondistance between the power dissipation and the registers. Supposing thatthe coordinates of the two registers are (x1, y1) and (x2, y2),respectively, and then |x1−x2|+|y1−y2| is given for Manhattan Distancebetween the two registers.

In addition to the two conditions, as mentioned above, the limitationsof the total connection length of scan chain, namely total length ofdistance between registers, is considered. Again, seeing from thetechnologies, hereinbefore, a fixed value is given for the powerdissipation of each of the two registers in the scan chain, and hence toreduce the peak value of the power dissipation is to cut down the numberof times of the potential state conversion. It is considered in thepresent invention that the practical power dissipation value of registeris not fixed, so that a small number of times of potential stateconversion unnecessarily mean small power dissipation.

SUMMARY OF THE INVENTAION

The test pattern data is in a proper order input from the outside of thescan chain into the inside of each of the registers for testing thecombinatory logic circuit. When an N-class register is included in ascan chain, the test pattern data must pass through N clock period toshift its value in a proper order and to store the test pattern data ina corresponding one of the registers. In this process, the shift maycause power dissipation when one of the states, 0-1 or 1-0, of the shiftregisters is changed.

This method of the present invention is to re-order the correspondingpositions of each of the registers on the scan chain for reduction ofthe peak power dissipation. The algorithm tool according to the presentinvention not only can match with the current design flow for VLSIcircuit to fast determine the proper order of the registers on the scanchain, but also can meet 3 following design conditions: (1) peak valueof power dissipation at potential conversion of register, (2) themaximum value of total connection length of scan chain, and (3) themaximum value of connection distance between two adjacent registers. Thescan chain buffer data and the test pattern data are input, and finallyordered the scan chain buffer data and the test pattern data that meetall conditions are output.

This method of the present invention, hereinbefore, is characterizedthat (1) an integrated data structure storing buffer and various delayinformation are built to facilitate data access in the process ofprogram computation, and (2) a Feasible Solution of a Clock Tree can bepromptly determined, wherein If the Clock Tree is not provided with anyfeasible solution, the optimum algorithm will not be performed any more,and the determined results are output for reference, (3) some Heuristicconcepts instead of Exhaustive Search algorithm are applied to solve theproblem, thereby saving time for optimal solution, and (4) within therange allowable by equipment, the algorithm tool according to thepresent invention is capable of processing a quite large circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a simple embodiment illustrating a scan chain beforearranged;

FIG. 1B shows a simple embodiment illustrating a scan chain afterarranged;

FIG. 2 shows an IC design and layout flow chart according to aconventional technology;

FIG. 3 shows an I/O block diagram of an algorithm tool according to aparticular embodiment of the present invention; and

FIG. 4 shows a flow chart explaining a database of registers adjacent toeach other according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 2 shows an IC design and layout flow chart according to aconventional technology. Step 1 for placement and step 4 for winding arethe traditional IC layout steps, wherein timing and noise optimizationcan be considered together. At step 2, Clock Tree Synthesis is performedto meet Clock Delay and Clock Skew. Next, at step 3, the scan chainre-ordering is performed. At this time, all circuits layout iscompleted, the scan chain registers are arranged in order according toonly design specification, and the finally winding is performed.

FIG. 3 shows an I/O block diagram of an algorithm tool according to aparticular embodiment in accordance with the present invention. The scanchain register circuit data 301 defines the name of each of theregisters, the 2D coordinates, and the power dissipation value. The 2Dcoordinates can provide Manhattan distance for algorithm. After a unitof test pattern data being input, every time a shift is made, and thenthe total power dissipation of the registers of which the potential isconverted and calculated until the test pattern shift stops and then thepeak value of power dissipation is gained. In the test pattern data 303of scan chain, if an M unit of the test pattern data is provided, themaximum is picked again from the peak values of the corresponding M-unitpower dissipation.

For simplicity, it is supposed in the present invention that (1) thedefaults of the potential state of each of the registers are 0 before afirst unit of the test pattern data is input, and (2) after the formerunit of test pattern data being completely shifted and output, thevalues of each of the registers are equal to those of registers at theinput of scan chain, and at this time another unit of new test patterndata is input. We assume that an algorithm of the power dissipation isperformed only when the potential conversion occurs in scan chain. Threelimited conditions are set in the design specification for data 305: (1)peaking value of the power dissipation at the time of potentialconversion of register, (2) the maximum of total connection length ofscan chain, and (3) the maximum of connection distance between twoadjacent registers.

Generally speaking, the Exhaustive Search is quite easy to get anoptimal solution; that is to say, all registers are sequentiallyarranged and a unit of the optimal arrangement order is found to meetall the limited conditions. However, the main disadvantages are thecases that (1) N! type(s) of arrangements are provided for N unit(s) ofregisters, and the maximum power dissipation must be compared with eacharrangement, so that the algorithm is largely complicated, and (2) Ifthere is no feasible solution that meets the limited condition(s), thedetermination is not made until the N! type(s) of the arrangement(s)is/are implemented.

As described above, fore regarding the problem, the developed algorithmtool according to the present invention provides as possibly as it canprompt the determination of a feasible solution, and quick and effectivesearch for an optimal solution. The main step of the algorithm toolincludes three items as follow:

-   -   1. According to the maximum limited distance between the two        adjacent registers, first at step 1, in FIG. 3, it is determined        whether a Feasible Solution meeting the limit condition is        provided. If any, at step 2, in FIG. 3, each register is        adjacent to a register that is searched, and a database is built        to store the information. If none, no feasible solution 321        meeting the condition is provided;    -   2. An event 311 impossibly meets the maximum limited distance        and the maximum, and the total length of the scan chain is        deleted; and    -   3. For the given test pattern, the arrangement order 313 of the        register on the scan chain is made for a reduction of the peak        value of the power dissipation, and it is determined whether the        peak value limit of the power dissipation and the limit        condition 315 of maximum total length for scan chain connection        accord. If yes, the updated scan chain arrangement 317 and the        corresponding scan chain test pattern data 319 are output, and        If not, no feasible solution 321 meeting the limit condition of        design is provided.

The present invention will be described in more details hereinafter.

Establishment of a Database of Register Adjacent to Each Other

A memory space is used to build a register database that meets themaximum distance between the two registers adjacent to each other. Inthe course of arrangement of each of the registers, the registerspossibly adjacent to each other are determined according to the limitcondition. If there are a large number of the registers in the scanchain, it takes much time in one-by-one search. Therefore, it isrequired to pre-build a group database of registers adjacent to eachother. At the time of the arrangement, the search field can be narrowed,thereby saving much time in search.

To effectively build a database, the following three stages will pass inthe processes, as shown in FIG. 4.

-   -   1. The distributed areas on the coordinates of all registers are        divided into the form of grid, and a grid 403 attributed to each        register is stored; use D representing the maximum limit of the        distance between two registers that are adjacent to each other.        The distributed areas of registers are divided into grids of 2D        in length and width. When a scan chain register file is read,        the coordinates of each of the registers are saved at the same        time. In addition, the positions of each of the registers in the        grid are unnecessarily fixed in the center so that the two        adjacent registers are possibly in the circumference of the grid        and their coordinates must also be saved. For example, in case        of D=5, if the register coordinates are (37, 52), then the        register stays in a grid (4, 6). Said register stays at lower        right-hand corner, so the corresponding adjacent registers be in        grids (5, 6), (4, 5), and (5, 5);    -   2. A register 405 falling in each grid is recorded; and    -   3. An adjacent registers group 407 according to the maximum        distance limit in the grid and in the circumference of the grid        is found and recorded.

However, if the maximum limit of the distance between the two adjacentregisters is over, it is not proper to build such a database for searchrequest. The higher maximum limit of distance is required, the more theregisters adjacent to each other is employed, and also the more the datamust be stored, the more the data is searched and the time is taken.Consequently, in the condition of invalid search, the memory space iswasted without any reason. Hereby, in order to solve this problem, inthe present invention based on the statistics, only when the amount ofgrid is larger than or equal to 9 (grids), a database of the adjacentregisters is built, or else, a search in an entire area will be made.

An Event Impossibly Meeting the Maximum Limited Distance and theMaximum, the Total Length of Scan Chain is Deleted.

First, an event impossibly meeting the maximum limit of distance isconsidered. According to the database of the adjacent registers that isbuilt in the former step, the following particular situations can beconcluded.

Existence in a register without any corresponding group of the adjacentregisters: indicates that the design is provided with no feasiblesolution. Existence in a register with only an adjacent registerindicates that the register must be the output terminal of this scanchain, and its adjacent register is second in arrangement order.

Existence in two registers with only an adjacent register: both of thetwo adjacent registers indicate no feasible solution is given. Forexample, if the register A1 is adjacent to the register A, then theregister B1 is adjacent to the register B. If A is B1, then it isinferred that A1 is B. Except A and B, no registers are adjacent so thatno solution is given.

Two registers are different from each other and indicate that oneregister can be made as the input of scan chain, and the other as theoutput.

At least four registers with only an adjacent register indicate that nofeasible solution is given. Except the I/O terminals of the scan chain,no places allow the register, so no feasible solution is given.

Next, the event not meeting the maximum, the total length limit of thescan chain is deleted. At this step, the best case and the worst caseare respectively estimated for the scan chain length. Regarding any ofthe registers I, the distance D_(i) ^(min) closer to the otherregisters, the distance D_(i) ^(max) further from the other registers,and the distance D_(i) ^(avg) equidistant from the other registers areestimated. If L^(min)=Σ_(i)D_(i) ^(min), L^(max)=Σ_(i)D_(i) ^(max), andL^(avg)=Σ_(i)D_(i) ^(avg) are made, then through the estimation, thescan chain length is given L^(min) for the best case, while the scanchain length is given L^(max) for the worst case. The actual scan chainlength is not probably L^(min) or L^(max), but the length falls withinthe two margins, so that a judgment can be made between the two margins.It is assumed that the total limit of the length of the maximum scanchain is L_(lim) and the two lengths are compared with each other forestimation, and then conclusion is made as follows:

-   -   L_(lim)<L^(min): no feasible solution given;    -   L^(min)<=L_(lim)<^(max): at the time of the arrangement of the        scan chain register at a next step, in addition to a search for        a combination of the peak values in the adjacent registers so as        to reduce power dissipation, a case beyond the total limit of        length of the maximum scan chain also being taken into        consideration so that registers must be arranged to shorten the        scan chain on the occasion; and    -   L^(lim)>L_(max): at the time of arrangement of the scan chain        registers at a next step, the total limit of length of the        maximum scan chain not being taken into consideration but a        search of a set of peak values in the adjacent registers to        reduce power dissipation.

Arrangement of the Registers on Scan Chain

When the shift of a test pattern on the scan chain is observed, it canbe found that more the register is close to the output of scan chain,the more groups of the shift registers of the opposite test pattern willpass by. Thus, the state conversion of register 0-1 or 1-0 may be causedfor many times in the course of the shift. In the algorithm toolaccording to the present invention, registers at the output of the scanchain are in advance set, and then the registers are recursivelyarranged in order towards the input terminal. The point is to decide anext optimal register to be arranged an optimal register of the outputterminal.

A peak value of the power dissipation is not given in the calculationuntil the registers on the entire scan chain is fully arranged, also,the calculation is enormous so that an actual value of the powerdissipation cannot be given in the course of recursive arrangement. Inthe aspect of the reduction of the power dissipation peak, it isexpected in the method of the present invention that the number of timesof the register state conversion caused in the period of shift isreduced, which is a concept on the statistics for an average in order toavoid an enormous peak value of the power dissipation at the time ofhuge state conversion. In order to reduce the calculation loading at thesame time, the algorithm tool according to the present invention uses alogical XOR calculation to every time sort out a next optimal registerin a set of registers having not been arranged in the course ofarrangement so that the opposite test patterns can be a little differentfrom the test patterns of registers so far having been arranged, therebyreducing the probability of register state conversion in each shift.

For example, the test patterns with respect to A, B, C, and D are listedbelow, and it is assumed that A has been arranged. A B C D 0 1 0 1 1 0 11 1 1 0 0 0 1 0 1 1 0 1 0

First, B, C, and D respectively corresponding to A are calculatedthrough XOR, and the minimum is used as an adjacent register of A. Incase of XOR(B,A)=4, XOR(C,A)=1, and XOR(D,A)=4, C is adjacent to A.Next, B and C respectively corresponding to C are calculated throughXOR, and the minimum is used as an adjacent register of C; in case ofXOR(B,C)=5 and XOR(D,C)=2, D is adjacent to C, and B is the last oneremaining. Thus, BDCA is the arrangement in order made from input tooutput on the scan chain.

Then, a selection of a register at the output terminal is considered.The test pattern opposite to the register at the output willcontinuously affect the state conversion of each of the shift registersand the arrangement of the scan chain. However, generally speaking, theycannot be tested one by one for a suitable register at the output.Hereon, some experiences are used to help in judgment.

According to the last step, the special case of the built adjacentregister database is used so that a register is existed with an adjacentregister only, and two registers are existed respectively with anadjacent register only and the two registers are different from theiradjacent registers.

If no special conditions occurred, the minority of the adjacentregisters among all registers is used as the registers at the output.Thus, in the case, the register cannot find an adjacent register in thescan chain is reduced, thereby facilitating the algorithm in timesaving.

No provision of an adjacent register database indicates that there is nostrict limit of the maximum distance between the adjacent registers, andthus the probability that the register cannot find any adjacent registerin scan chain is lower. At this time, of all registers, a register ofthe maximum power dissipation is used as an output terminal, and thatless different from the test pattern is used as an input terminal,thereby effectively lowering the impact of the register of maximum powerdissipation to the peak value of power dissipation through full design.

Other Special Cases

Some special cases happening in the foregoing algorithm cannot besolved, so that the conclusion is made below.

Ordering of the registers on the scan chain simply through the reductionof the peak value of the power dissipation only may be contrary to thelimit of the maximum scan chain length. To solve the problem, the timefor algorithm tool to order the scan chain must be determined best ofall through shortening of the distance to the registers forconformability with the limit of maximum length. In the preferredembodiment of the present invention, an experience is used forestimation.

After the registers being arranged each time through the results givenfrom algorithm with XOR, the remaining length compared with the maximumlength is estimated, the number of registers not arranged is divided,and finally, an average remaining distance is given.

Next, estimation of the margin around the average remaining distance isconsidered. The average estimation of the two proximal distanceD^(min)=L^(min)/Σ_(i)i is ideal, while average estimation of theaveraged distance D^(avg)=L_(avg)/Σ_(i)i is actual, thus, the minimumbetween 10*D^(min) and (D^(min)+D^(avg))/2 is taken in the method of thepresent invention for estimation. Once the averaged remaining distanceis less than the estimative value, the next registers are arranged veryadjacent to each other.

A case that the registers not arranged existing in any of the registersnot found adjacent intuitionally replace with another register. If noother registers exist, it is known that the arrangement of the formerone register or several registers arranged is not proper, thus, thesequence of the scan chain registers formerly have been arranged must beagain considered like DFS or Branch-and-Bound. However, in thisestimation, the algorithm loading and the memory space required are toolarge to deal with a scan chain with a great lot of registers. Thus, forfear of no adjacent registers not arranged, in addition to a nextregister selected through XOR, a register adjacent to maximum registersnot arranged must be found and recorded.

In short, in the present invention, a method of reordering a scan chainfor the design of testability on VLSI with low power dissipation isprovided to work with the current design flow for VLSI, to promptlydetermine the sequence of registers on a suitable scan chain, and tomeet three limited conditions in the design specification: (1) peakvalue of power dissipation at the time of potential conversion ofregister, (2) the maximum of total connection length of scan chain and(3) the maximum of connection distance between adjacent two registers.The main steps of performing the algorithm tool in accordance with thepresent invention include: to determine whether a Feasible Solutionmeeting the maximum limit of distance between the two registers adjacentto each other being provided, if yes, a database of registers adjacentto each other is built; if not, no feasible solution meeting the limitcondition of design is provided. An event impossibly meets the maximumlimited distance and the maximum and the total length of the scan chainis deleted. For the given test pattern, the registers on scan chain arere-ordered and it is determined whether the peak value limit of powerdissipation and the limit condition of maximum total length for scanchain connection accord, if yes, the updated scan chain arrangement andthe corresponding scan chain test pattern data are output; if not, nofeasible solution meeting the limit condition of design is provided.

As described above, only operational principles are given that does notlimit the present invention. Although the invention has been explainedin relation to its preferred embodiment, it is to be understood thatmany other possible modifications and variations can be made withoutdeparting from the spirit and scope of the invention as hereinafterclaimed.

1. A method of reordering a scan chain for the design of testability onVLSI with low power dissipation, comprising the following steps of: (a)inputting scan chain register circuit data, including the name of eachregister, a 2D coordinates, and power dissipation value(s); (b)inputting to test pattern data on the scan chain; (c) inputtingconditions of the design specification: (1) peak value of powerdissipation at the time of potential conversion of register; (2) themaximum of total connection length of scan chain; and (3) the maximum ofconnection distance between adjacent two registers; (d) determiningwhether a Feasible Solution meeting the maximum limit of distancebetween two adjacent registers is provided; (e) creating a database ofthe two adjacent registers; (f) an event impossibly meeting both themaximum limited distance and the maximum limited distance, and the totallength of the scan chain being deleted; (g) for the given test pattern,re-ordering the registers on the scan chain for reduction of powerdissipation, and it being determined whether the peak value limit ofpower dissipation and the limit condition of maximum total length forthe scan chain connection accord; and (h) outputting the updated scanchain arrangement and the corresponding scan chain test pattern data. 2.The method as claimed in claim 1, wherein steps of creating the databaseof the two adjacent registers includes:. (a) dividing the distributedareas on the coordinates of all registers into the form of grids, andstoring a grid attributed to each register; (b) recording a registerfalling in each grid; and (c) searching for a group of the two adjacentregisters according to the maximum distance limit in the grid and in thecircumference of the grid, and then recording them.
 3. The method asclaimed in claim 1, wherein an event impossibly meeting both the maximumlimited distance is deleted in the case of (a) existence in a registerwithout any corresponding group of the two adjacent registers:indicating that the design is provided with no feasible solution; (b)existence in a register with only an adjacent register: indicating thatthe register must be the output terminal of the scan chain, and itsadjacent register is second in arrangement order; (c) existence in tworegisters with only an adjacent register: i. both of the two adjacentregisters: indicating that no feasible solution is given; and ii. tworegisters different from each other: indicating that one register can bemade to be the input terminal of the scan chain, and the other, to bethe output terminal; and (d) at least four registers with only anadjacent register: indicating that no feasible solution is given.
 4. Themethod as claimed in claim 1, wherein an event impossibly meeting themaximum of total connection length of scan chain is deleted in the caseof (a) L_(lim)<L^(min): no feasible solution given; (b)L^(min)<=L_(lim)<L^(max): at the time of the arrangement of the scanchain register at a next step, in addition to a search for a combinationof the peak values in the adjacent registers so as to reduce powerdissipation, a case beyond the total limit of length of the maximum scanchain also being taken into consideration so that the registers must bearranged to shorten the scan chain on the occasion; and (c)L_(lim)>L^(max): at the time of arrangement of the scan chain registersat a next step, the total limit of length of the maximum scan chain notbeing taken into consideration but a search for a set of peak values inthe adjacent registers to reduce power dissipation; wherein i stands forany of the registers, and the distance D_(i) ^(min) indicates thedistance of a register i closer to the other registers, the distanceD_(i) ^(max) indicates the distance of a register i further from theother registers, and the distance D_(i) ^(avg) indicates the distance ofa register i equidistant from the other registers are estimated, namelyL^(min)=Σ_(i)D_(i) ^(min), L^(max)=Σ_(i)D_(i) ^(max), andL^(avg)=Σ_(i)D_(i) ^(avg).
 5. The method of reordering a scan chain forthe design of testability on VLSI with low power dissipation as claimedin claim 1, wherein scan chain registers are reordered to (a) decide anext optimal register to be arranged; and (b) decide an optimal registerof the output terminal.
 6. The method of reordering a scan chain for thedesign of testability on VLSI with low power dissipation as claimed inclaim 5, wherein in order to decide a next optimal register to bearranged, the algorithm tool according to this invention uses a logicalXOR calculation to every time sort out a next optimal register in a setof registers having not been arranged in the course of arrangement sothat the opposite test patterns can be little different from the testpatterns of registers so far having been arranged, thereby reducing theprobability of register state conversion in each shift.
 7. The method ofreordering a scan chain for the design of testability on VLSI with lowpower dissipation as claimed in claim 3, wherein in order to decide anoptimal register of the output terminal after the scan chain registersreordered includes: (a) the special case of the built database ofregisters adjacent to each other occurs when (1) a register is existedwith an adjacent register only; and (2) two registers are existedrespectively with an adjacent register only, and the two registers aredifferent from their adjacent registers; (b) when no special casesoccur, the minority of adjacent registers among all registers is used asthe registers at the output; and (c) when a database of registersadjacent to each other is provided, of all registers, a register ofmaximum power dissipation is used as an output terminal, and that lessdifferent from the test pattern is used as an input terminal.